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Pro-Form ZE5 Especificaciones Pagina 24

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Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 24
Routing
Matrix
Routing
Matrix
Routing
Matrix
Routing
Matrix
CSL Cell
CSL Cell
8 Short Segments
8 Short Segments
8 Short Segments
8 Short Segments
8 Long Lines
4 Clock/Global Buffers
4 Clock/Global Buffers
8 Long Lines
4 Clock/Global Buffer
8 Long Lines
Selector outputs
from vertical breaker
Selector outputs
from vertical breaker
Address outputs
from horizontal breaker
Carry,
cascaded
wide function
path
Carry,
cascaded
wide function
path
Figure 22. The general-purpose interconnect surrounds a pair of adjacent CSL cells.
Routing
Matrix
Routing
Matrix
Routing
Matrix
Routing
Matrix
CSL Cell
CSL Cell
8 Short Segments
8 Short Segments
8 Short Segments
8 Short Segments
8 Long Lines
4 Clock/Global Buffers
4 Clock/Global Buffers
8 Long Lines
CSI Data Write
CSI Data Write
4 Clock/Global Buffer
OR
OR
CSI Data Read
8 Long Lines
4 Mux Chains
4 Mux Chains
Figure 23. CSI bus write data is available at each routing matrix. Read data returns to the CSI bus.
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