Pro-Form ZE5 Especificaciones Pagina 48
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Valorado. / 5. Basado en revisión del cliente
Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 48
Configuration Register Unit (CRU)
The Configuration Register Unit (CRU) contains
the control registers for functions within the Zylogic
ZE5 configurable system-on-chip. For most appli-
cations, the CRU registers occupy the upper 256
bytes of external data space.
Table 24 shows the functions controlled by the
CRU registers. Unused locations have no function
and are not RAM locations.
System Initialization
Like most processors, the Zylogic ZE5 requires
initialization data to configure programmable op-
tions available within the device before it becomes
functional. The Zylogic ZE5 offers four different
system initialization options to best fit various tar-
get applications, as shown in Table 25. Both ac-
tive and passive initialization methods are avail-
able.
In active initialization modes, the Zylogic ZE5 pro-
vides the control signals, directing data transfers
and controlling external devices.
In passive modes, an external controller directs
data transfers.
Table 25. Initialization Modes.
Initialization
Mode Method Data Source
Parallel Active
Byte-wide parallel
memory (FLASH)
Serial Active
Sequential-access
serial PROM
Secure Active
Battery-backed in-
ternal SRAM
JTAG Passive
Downloaded by in-
telligent host
through JTAG port
Table 24. Configuration Register Unit (CRU).
FF88h DMAP5_SRC DMAP5_CTL
FF80h
DMAP4_TAR_0
[7:0]
DMAP4_TAR_1
[15:8]
DMAP4_TAR_2
[23:16]
DMAP4_SRC DMAP4_CTL
DMAP5_TAR_0
[7:0]
DMAP5_TAR_1
[15:8]
DMAP5_TAR_2
[23:16]
FF78h
FF70h
FF68h
FF60h
PROTECT SECURITY PWDSEL PORCTRL
FF58h
FF50h
FF48h
DMACRC_0
[7:0]
DMACRC_1
[15:8]
FF40h
DMACADR1_1
[15:8]
DMACADR1_2
[23:16]
DMACADR1_3
[31:24]
DMACCNT1_0
[7:0]
DMACCNT1_1
[15:8]
DMACCNT1_2
[23:16]
DMAPREQ1_0
[7:0]
DMAPREQ1_1
[15:8]
FF38h
DMASCNT1_0
[7:0]
DMASCNT1_1
[15:8]
DMASCNT1_2
[23:16]
DMACTRL1_0
[7:0]
DMACTRL1_1
[15:8]
DMAEINT1 DMAINT1
DMACADR1_0
[7:0]
FF30h
DMACCNT0_1
[15:8]
DMACCNT0_2
[23:16]
DMAPREQ0_0
[7:0]
DMAPREQ0_1
[15:8]
DMASADR1_0
[7:0]
DMASADR1_1
[15:8]
DMASADR1_2
[23:16]
DMASADR1_3
[31:24]
FF28h
DMACTRL0_1
[15:8]
DMAEINT0 DMAINT0
DMACADR0_0
[7:0]
DMACADR0_1
[15:8]
DMACADR0_2
[23:16]
DMACADR0_3
[31:24]
DMACCNT0_0
[7:0]
FF20h
DMASADR0_0
[7:0]
DMASADR0_1
[15:8]
DMASADR0_2
[23:16]
DMASADR0_3
[31:24]
DMASCNT0_0
[7:0]
DMASCNT0_1
[15:8]
DMASCNT0_2
[23:16]
DMACTRL0_0
[7:0]
FF18h
DMAP2_CTL DMAP3_TAR DMAP3_SRC DMAP3_CTL
FF10h
DMAP1_TAR_1
[15:8]
DMAP1_TAR_2
[23:16]
DMAP1_SRC DMAP1_CTL
DMAP2_TAR_0
[7:0]
DMAP2_TAR_1
[15:8]
DMAP2_TAR_2
[23:16]
DMAP2_SRC
FF08h
CMAP2_TAR_0
[7:0]
CMAP2_TAR_1
[15:8]
CMAP2_TAR_2
[23:16]
CMAP2_SRC CMAP2_CTL CMAP2_ALT DMAP0_TAR
DMAP1_TAR_0
[7:0]
FF00h
CMAP0_TAR CMAP0_ALT
CMAP1_TAR_0
[7:0]
CMAP1_TAR_1
[15:8]
CMAP1_TAR_2
[23:16]
CMAP1_SRC CMAP1_CTL CMAP1_ALT
Unused location, not RAM.
- Zylogic ZE5 Configurable 1
- System-on-Chip Platform 1
- Overview 3
- Triscend 4
- Configurable 4
- System-on-Chip 4
- DMA Controller 6
- 76543210 10
- ADRM1 ADRM0 11
- Data Write 19
- Data Read 20
- TE505 (2x2) 22
- TE512 (3x3) 22
- TE520 (4x4) 22
- TE532 (5x5) 22
- TE502 (2x1) 22
- 27 www.zylogic.com.cn 27
- Dual-Port 29
- Mode D ClkEna Clock Q 32
- Memory Interface Unit 34
- SETUP STROBE HOLD 35
- SETUP STROBE 36
- Address Mappers 38
- Mask = 2 40
- BLOCK_SIZE 40
- A15 A14 A13 A12 A11 A10 A9 A8 42
- Configurable System-on-Chip 47
- System Initialization 48
- Triscend E5 49
- External Parallel Memory 49
- (optional) 50
- Upper Address 50
- Application Dependent 50
- (Slave Mode) 51
- External Controller or 51
- Master E5 CSoC 51
- Clock input signal 54
- (Reads = 0) 58
- EA - ET2 ES ET1 EX1 ET0 EX0 60
- - - PT2 PS PT1 PX1 PT0 PX0 61
- - - - - - - - DCEN 62
- CY AC F0 RS1 RS0 OV F1 P 62
- Instruction Set 64
- Interrupts 66
- (highest) 67
- (lowest) 67
- Reset Conditions 69
- Power Management 71
- - -PIOXTALOSCGBUF 72
- - ------PORCT 72
- Glossary 74
- Life Support Policy 74
- Revision List 74
- 75 www.zylogic.com.cn 75
- Pin Description 76
- Pinout Diagrams and Tables 79
- TE502S08L 80
- TE505S16L 80
- TE512S32L 80
- Top View 83
- TE505S16Q 84
- TE512S32Q 84
- TE520S40Q 84
- TE532S64Q 84
- TE520S40B 89
- 91 www.zylogic.com.cn 91
- Bottom View 93
- 35 pF12 mA 96
- [1] Max Max 98
- External 99
- Byte-wide 99
- C1 C2 C3 C4 C4 C1 100
- www.zylogic.com.cn 101
- Start Here 102
- Bus Clock 104
- Flip-flop 108
- BCLK/XTAL 115
- BusClock 115
- Output Voltage (V) 118
- Output Current (mA) 118
- TE5 20 S 40 - 40 Q C 119
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